SH7144_08 Datasheet, PDF (917/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

Main Revisions for this Edition
Main Revisions for this Edition
Item
Page Revision (See Manual for Details)
5.1.3 Exception
64
Processing Vector Table
Table 5.3 Exception
Processing Vector Table
Table and note amended
Exception Sources
Vector Numbers Vector Table Address Offset
On-chip peripheral module*²
72
H'00000120 to H'00000123
:
:
255
H'000003FC to H'000003FF
Notes: 1. Only in the F-ZTAT version.
2. The vector numbers and vector table address offsets for each on-chip peripheral
module interrupt are given in table 6.2.
11.4.5 PWM Modes
275 Figure amended
Figure 11.23 Example of
PWM Mode Operation (3)
TCNT value
TGRA
TGRB rewritten
Output does not change when cycle register and duty register
compare matches occur simultaneously
TGRB
H'0000
TGRB rewritten
TGRB rewritten
Time
TIOCA
100% duty
11.4.8 Complementary
PWM Mode
Figure 11.34
Complementary PWM
Mode Counter Operation
290
Figure amended
Counter value
TGRA_3
TCDR
TDDR
H'0000
TCNT_3
TCNT_4 _TCNTS
TCNT_3
TCNT_4
TCNTS
Time
Rev.4.00 Mar. 27, 2008 Page 873 of 882
REJ09B0108-0400