SH7144_08 Datasheet, PDF (13/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

9.5 Register Descriptions ........................................................................................................144
9.5.1 Bus Control Register 1 (BCR1) ...........................................................................144
9.5.2 Bus Control Register 2 (BCR2) ...........................................................................147
9.5.3 Wait Control Register 1 (WCR1).........................................................................152
9.5.4 Wait Control Register 2 (WCR2).........................................................................153
9.5.5 RAM Emulation Register (RAMER)...................................................................153
9.6 Accessing External Space .................................................................................................154
9.6.1 Basic Timing........................................................................................................154
9.6.2 Wait State Control................................................................................................155
9.6.3 CS Assert Period Extension .................................................................................157
9.7 Waits between Access Cycles...........................................................................................158
9.7.1 Prevention of Data Bus Conflicts.........................................................................158
9.7.2 Simplification of Bus Cycle Start Detection ........................................................160
9.8 Bus Arbitration..................................................................................................................161
9.9 Memory Connection Example ..........................................................................................163
9.10 Access to On-chip Peripheral I/O Registers......................................................................166
9.11 Cycles of No-Bus Mastership Release ..............................................................................166
9.12 CPU Operation when Program Is Located in External Memory.......................................166
Section 10 Direct Memory Access Controller (DMAC) .................................. 167
10.1 Features .............................................................................................................................167
10.2 Input/Output Pins ..............................................................................................................169
10.3 Register Descriptions ........................................................................................................170
10.3.1 DMA Source Address Registers_0 to 3 (SAR_0 to SAR_3) ...............................170
10.3.2 DMA Destination Address Registers_0 to 3 (DAR_0 to DAR_3).......................171
10.3.3 DMA Transfer Count Registers_0 to 3 (DMATCR_0 to DMATCR_3)..............171
10.3.4 DMA Channel Control Registers_0 to 3 (CHCR_0 to CHCR_3)........................172
10.3.5 DMAC Operation Register (DMAOR) ................................................................178
10.4 Operation...........................................................................................................................180
10.4.1 DMA Transfer Flow ............................................................................................180
10.4.2 DMA Transfer Requests ......................................................................................182
10.4.3 Channel Priority ...................................................................................................184
10.4.4 DMA Transfer Types ...........................................................................................187
10.4.5 Number of Bus Cycle States and DREQ Pin Sample Timing..............................197
10.4.6 Source Address Reload Function .........................................................................203
10.4.7 DMA Transfer Ending Conditions.......................................................................204
10.4.8 DMAC Access from CPU....................................................................................205
10.5 Examples of Use ...............................................................................................................206
10.5.1 Example of DMA Transfer between On-Chip SCI and External Memory ..........206
Rev.4.00 Mar. 27, 2008, Page xiii of xliv
REJ09B0108-0400