SH7144_08 Datasheet, PDF (575/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
Table 14.10 I²C Bus Timing (when the effect of t_Sr/t_Sf Is at its maximum)
Time (at Maximum Transfer Rate) [ns]
Item t_pcyc
Effect I²C bus
of t_Sr/t_Sf specification Pφ= Pφ= Pφ= Pφ= Pφ= Pφ=
(max) (min)
10MHz 16MHz 20MHz 25MHz 33MHz 40MHz
t
SCLHO
0.5 t_SCLO
(−t )
Sr
Standard
mode
-1000
High-speed -300
mode
4000
600
4000 4000 4000 4000 4000 4000
950
950
950
950
950
950
t
SCLLO
0.5 t
SCLO
(−t )
Sf
Standard
mode
-250
High-speed -250
mode
4700
1300
4750 4750 4750 4750 4750 4750
1000*¹ 1000*¹ 1000*¹ 1000*¹ 1000*¹ 1000*¹
t_BUFO
0.5 t −1 t
SCLO
pcyc
Standard
-1000
4700
(−t )
Sr
mode
High-speed -300
1300
mode
3900*¹ 3938*¹ 3950*¹ 3960*¹ 3970*¹ 3975*¹
850*¹ 888*¹ 900*¹ 910*¹ 920*¹ 925*¹
t
STAHO
0.5 t −1 t
SCLO
pcyc
(−t )
Sf
Standard
mode
-250
High-speed -250
mode
4000
600
4650 4688 4700 4710 4720 4725
900
938
950
960
970
975
t
STASO
1t
SCLO
(−t )
Sr
Standard
mode
-1000
High-speed -300
mode
4700
600
9000 9000 9000 9000 9000 9000
2200 2200 2200 2200 2200 2200
t_STOSO
0.5 t +2 t
SCLO
pcyc
(−t )
Sr
t
SDASO
As
1
t *3
SCLLO
−3
t
pcyc
(−t_Sr)
master
Standard
mode
-1000
High-speed -300
mode
Standard
mode
-1000
High-speed -300
mode
4000
600
250
100
4200 4125 4100 4080 4061 4050
1150 1075 1050 1030 1011 1000
3400 3513 3550 3580 3609 3625
700
813
850
880
909
925
t
SDASO
As
1
t *3
SCLL
−12
t *2
pcyc
Standard
(−t )
Sr
mode
-1000
250
slave
High-speed -300
100
mode
2500 2950 3100 3220 3336 3400
-200*¹ 250
400
520
636
700
t
SDAHO
3t
pcyc
Standard 0
0
mode
300
188
150
120
91
75
High-speed 0
0
mode
300
188
150
120
91
75
Rev.4.00 Mar. 27, 2008 Page 531 of 882
REJ09B0108-0400