SH7144_08 Datasheet, PDF (69/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

2. CPU
2.4.2 Addressing Modes
Table 2.8 describes addressing modes and effective address calculation.
Table 2.8 Addressing Modes and Effective Addresses
Addressing
Mode
Instruction
Format
Effective Address Calculation
Equation
Direct register Rn
addressing
The effective address is register Rn. (The operand —
is the contents of register Rn.)
Indirect register @Rn
addressing
The effective address is the contents of register Rn. Rn
Rn
Rn
Post-increment @Rn+
indirect register
addressing
The effective address is the contents of register Rn. Rn
A constant is added to the content of Rn after the
instruction is executed. 1 is added for a byte
operation, 2 for a word operation, and 4 for a
longword operation.
(After the
instruction
executes)
Byte:
Rn
Rn
Rn + 1 → Rn
Rn + 1/2/4 ₊
Word:
Rn + 2 → Rn
1/2/4
Longword:
Rn + 4 → Rn
Pre-decrement @-Rn
indirect register
addressing
The effective address is the value obtained by
subtracting a constant from Rn. 1 is subtracted for
a byte operation, 2 for a word operation, and 4 for
a longword operation.
Rn
Rn – 1/2/4 _–
Rn – 1/2/4
1/2/4
Byte:
Rn – 1 → Rn
Word:
Rn – 2 → Rn
Longword:
Rn – 4 → Rn
(Instruction is
executed with
Rn after this
calculation)
Rev.4.00 Mar. 27, 2008 Page 25 of 882
REJ09B0108-0400