SH7144_08 Datasheet, PDF (260/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

11. Multi-Function Timer Pulse Unit (MTU)
Input/output pins
Channel 3: TIOC3A
TIOC3B
TIOC3C
TIOC3D
Channel 4: TIOC4A
TIOC4B
TIOC4C
TIOC4D
Interrupt request signals
Channel 3: TGIA_3
TGIB_3
TGIC_3
TGID_3
TCIV_3
Channel 4: TGIA_4
TGIB_4
TGIC_4
TGID_4
TCIV_4
Clock input
Internal clock: ^Pφ/1
Pφ/4
Pφ/16
Pφ/64
Pφ/256
Pφ/1024
External clock: ^TCLKA
TCLKB
TCLKC
TCLKD
Input/output pins
Channel 0: TIOC0A
TIOC0B
TIOC0C
TIOC0D
Channel 1: TIOC1A
TIOC1B
Channel 2: TIOC2A
TIOC2B
Internal data bus
A/D converter conversion
start signal
Interrupt request signals
Channel 0: TGIA_0
TGIB_0
TGIC_0
TGID_0
TCIV_0
Channel 1: TGIA_1
TGIB_1
TCIV_1
TCIU_1
Channel 2: TGIA_2
TGIB_2
TCIV_2
TCIU_2
[Legend]
TSTR:
Timer start register
TIER:
TSYR:
Timer synchro register
TSR:
TCR:
Timer control register
TCNT:
TMDR:
Timer mode register
TGR (A, B, C, D):
TIOR (H, L): Timer I/O control registers (H, L)
Timer interrupt enable register
Timer status register
Timer counter
Timer general registers (A, B, C, D)
Figure 11.1 Block Diagram of MTU
Rev.4.00 Mar. 27, 2008 Page 216 of 882
REJ09B0108-0400