SH7144_08 Datasheet, PDF (179/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

8. Data Transfer Controller (DTC)
8.4.3 DTC Use Example
The following is a DTC use example of a 128-byte data reception by the SCI:
1. The settings are: DTMR source address fixed (SM1 = SM0 = 0), destination address
incremented (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), byte size (SZ1 = SZ0 =
0), one transfer per activating source (CHNE = 0), and a CPU interrupt request after the
designated number of data transfers (DISEL = 0). DTS bit can be set to any value. 128
(H'0080) is set in DTCRA, the RDR address of the SCI is set in DTSAR, and the start address
of the RAM storing the receive data is set in DTDAR. DTCRB can be set to any value.
2. Set the register information start address with DTBR and the DTC vector table.
3. Set the corresponding DTER bit to 1.
4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception
complete (RXI) interrupt. Since the generation of a receive error during the SCI reception
operation will disable subsequent reception, the CPU should be enabled to accept receive error
interrupts.
5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an
RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR
to RAM by the DTC. DTDAR is incremented and DTCRA is decremented. The RDRF flag is
automatically cleared to 0.
6. When DTCRA is 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the
corresponding bit in DTER is cleared to 0, and an RXI interrupt request is sent to the CPU.
The interrupt handling routine should perform completion processing.
Rev.4.00 Mar. 27, 2008 Page 135 of 882
REJ09B0108-0400