SH7144_08 Datasheet, PDF (247/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

10. Direct Memory Access Controller (DMAC)
10.4.6 Source Address Reload Function
Channel 2 has a source address reload function. This returns to the first value set in the source
address register (SAR_2) every four transfers by setting the RO bit of CHCR_2 to 1. Figure 10.24
illustrates this operation. Figure 10.25 is a timing chart for reload ON mode, with burst mode,
autorequest, 16-bit transfer data size, SAR_2 increment, and DAR_2 fixed mode.
DMAC
DMAC control block
Transfer
request
Reload control
4th count
RO bit = 1
CHCR_2
Count signal
DMATCR_2
Reload signal
Reload
signal
SAR_2
(initial value)
SAR_2
Figure 10.24 Source Address Reload Function
CK
Internal
address bus
Internal
data bus
SAR2 DAR2 SAR2+2 DAR2 SAR2+4 DAR2 SAR2+6 DAR2
SAR2 data
SAR2+2 data SAR2+4 data SAR2+6 data
SAR2 DAR2
SAR2 data
1st channel 2
transfer
SAR2 output
DAR2 output
2nd channel 2
transfer
3rd channel 2
transfer
4th channel 2
transfer
SAR2+2 output SAR2+4 output SAR2+6 output
DAR2 output DAR2 output DAR2 output
5th channel 2
transfer
SAR2 output
DAR2 output
After SAR2+6 output, SAR2 is reloaded Bus mastership is returned one time in four
Figure 10.25 Source Address Reload Function Timing Chart
Rev.4.00 Mar. 27, 2008 Page 203 of 882
REJ09B0108-0400