SH7144_08 Datasheet, PDF (891/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

D. I/O Port Block Diagrams
RES
R
Q PEnDR D
C
PEDRL.WR
Function 2
TIOCxx (MTU)
PEDRL.RD
TIOCxx (MTU)
PFC
Q PEnMD0
Q PEnMD1
Q PEnIOR
Software standby
SBYCR
Q Hi-Z
RES: Reset signal
PEDRL.RD: Port E data register L read signal
PEDRL.WR: Port E data register L write signal
Figure D.35 PEn/TIOCxx/Function 2
Pins
PE1/TIOC0B/
DRAK0
PE3/TIOC0D/
DRAK1
PE5/TIOC1B/
TXD3
PE10/TIOC3C/
TXD2
Symbol in Figure D.35
Available Products
SH7144
SH7145
Masked ROM
Masked ROM
version/
version/
Function F-ZTAT ROM less
F-ZTAT ROM less
PEn TIOCxx 2
version version
version version
PE1 TIOC0B DRAK0 ⎯
√
(MTU) (DMAC)
⎯
√
PE3 TIOC0D DRAK1 ⎯
√
(MTU) (DMAC)
⎯
√
PE5 TIOC1B TXD3
√
√
(MTU) (SCI)
⎯
√
PE10 TIOC3C TXD2
√
√
(MTU) (SCI)
⎯
√
Rev.4.00 Mar. 27, 2008 Page 847 of 882
REJ09B0108-0400