SH7144_08 Datasheet, PDF (25/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

Figures
Section 1 Overview
Figure 1.1 Internal Block Diagram of SH7144...............................................................................4
Figure 1.2 Block Diagram of SH7145 ............................................................................................5
Figure 1.3 SH7144 Pin Arrangement..............................................................................................6
Figure 1.4 SH7145 Pin Arrangement..............................................................................................7
Section 2 CPU
Figure 2.1 CPU Internal Registers ................................................................................................16
Figure 2.2 Data Format in Registers .............................................................................................19
Figure 2.3 Data Formats in Memory.............................................................................................19
Figure 2.4 Transitions between Processing States ........................................................................45
Section 3 MCU Operating Modes
Figure 3.1 Address Map for Each Operating Mode......................................................................51
Figure 3.2 Reset Input Timing when Changing Operating Mode.................................................52
Section 4 Clock Pulse Generator
Figure 4.1 Block Diagram of Clock Pulse Generator ...................................................................53
Figure 4.2 Connection of Crystal Resonator (Example) ...............................................................55
Figure 4.3 Crystal Resonator Equivalent Circuit ..........................................................................55
Figure 4.4 Example of External Clock Connection ......................................................................56
Figure 4.5 Cautions for Oscillator Circuit Board Design..............................................................58
Figure 4.6 Recommended External Circuitry around PLL ...........................................................59
Section 6 Interrupt Controller (INTC)
Figure 6.1 INTC Block Diagram ..................................................................................................78
Figure 6.2 Block Diagram of IRQ7 to IRQ0 Interrupts Control ...................................................88
Figure 6.3 Interrupt Sequence Flowchart......................................................................................94
Figure 6.4 Stack after Interrupt Exception Processing..................................................................95
Figure 6.5 Example of Pipeline Operation when IRQ Interrupt Is Accepted ...............................97
Figure 6.6 Interrupt Control Block Diagram ................................................................................98
Section 7 User Break Controller (UBC)
Figure 7.1 User Break Controller Block Diagram ......................................................................102
Figure 7.2 Break Condition Determination Method ...................................................................107
Section 8 Data Transfer Controller (DTC)
Figure 8.1 Block Diagram of DTC .............................................................................................114
Figure 8.2 Activating Source Control Block Diagram................................................................122
Figure 8.3 DTC Register Information Allocation in Memory Space..........................................123
Figure 8.4 Correspondence between DTC Vector Address and Transfer Information ...............123
Rev.4.00 Mar. 27, 2008, Page xxv of xliv
REJ09B0108-0400