SH7144_08 Datasheet, PDF (536/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
14.3.8 ICDRE Flag (Internal Flag)
The ICDRE flag is set and cleared under the conditions as shown below. Since the ICDRE flag is
an internal flag, it cannot be accessed.
Bit Name Initial Value
ICDRE 0
Description
Transmit Data Write Request Flag
This flag is an internal flag that indicates the ICDR (ICDRT) state in
transmission mode.
0: Indicates that the data to be transmitted has been already written to
ICDR (ICDRT) or ICDR is initialized.
1: Indicates that data has been transferred from ICDRT to ICDRS and
is being transmitted, or the start condition has been detected or
transmission has been completed, thus allowing the next data to be
written to.
[Setting conditions]
• When the start condition is detected from the bus line state in I²C
bus format or serial format.
• When data is transferred from ICDRT to ICDRS.
A. When data transmission is completed while ICDRE =0 (at the
rising edge of the 9th cycle of the clock).
B. When ICDR is written to in transmit mode after data
transmission is completed while ICDRE = 1.
[Clearing conditions]
• When transmit data is written to ICDR (ICDRT).
• When the stop condition is detected in I²C bus format or serial
format.
• When 0 is written to the ICE bit.
Note that if the ACKE bit is set to 1 in I²C bus format thus enabling
acknowledge bit decision, ICDRE is not set when data transmission is
completed while the acknowledge bit is 1.
Due to the set condition B above, ICDRE is temporarily cleared to 0
when data is written to ICDR (ICDRT); however, since data is
transferred from ICDRT to ICDRS immediately, ICDRE is set to 1
again. Do not write data to ICDR when TRS = 0 because the ICDRE
flag value is invalid during the time.
Rev.4.00 Mar. 27, 2008 Page 492 of 882
REJ09B0108-0400