SH7144_08 Datasheet, PDF (74/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

2. CPU
Instruction Formats
nm format
15
0
xxxx nnnn mmmm xxxx
md format
15
0
xxxx xxxx mmmm dddd
nd4 format
15
xxxx xxxx
0
nnnn dddd
nmd format
15
0
xxxx nnnn mmmm dddd
Source
Operand
Destination
Operand
mmmm: Direct
register
nnnn: Direct
register
mmmm: Direct
register
nnnn: Indirect
register
mmmm: Indirect
post-increment
register (multiply-
and-accumulate)
nnnn*: Indirect
post-increment
register (multiply-
and-accumulate)
MACH, MACL
mmmm: Indirect
post-increment
register
nnnn: Direct
register
mmmm: Direct
register
nnnn: Indirect pre-
decrement
register
mmmm: Direct
register
nnnn: Indirect
indexed register
mmmmdddd:
R0 (Direct
Indirect register with register)
displacement
Example
ADD Rm,Rn
MOV.L Rm,@Rn
MAC.W
@Rm+,@Rn+
MOV.L @Rm+,Rn
MOV.L Rm,@-Rn
MOV.L
Rm,@(R0,Rn)
MOV.B
@(disp,Rn),R0
R0 (Direct register) nnnndddd:
MOV.B
Indirect register with R0,@(disp,Rn)
displacement
mmmm: Direct
register
nnnndddd: Indirect
register with
displacement
mmmmdddd:
nnnn: Direct
Indirect register with register
displacement
MOV.L
Rm,@(disp,Rn)
MOV.L
@(disp,Rm),Rn
Rev.4.00 Mar. 27, 2008 Page 30 of 882
REJ09B0108-0400