SH7144_08 Datasheet, PDF (438/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

13. Serial Communication Interface (SCI)
Clocked synchronous mode
• Data length: 8 bits
• Receive error detection: Overrun errors detected
Smart card interface
• Data is automatically retransmitted if an error signal is received while data is being transmitted
• Direct convention and inverse convention both supported
Note: * The description in this section is based on LSB-first transfer.
Figure 13.1 shows a block diagram of the SCI.
Module data bus
Internal
data bus
RxD
TxD
SCK
RDR
RSR
TDR
SSR
BRR
SCR
TSR
SMR
SDCR
Transmission/
reception
control
Baud rate
generator
Parity generation
Clock
Parity check
External clock
[Legend]
RSR: Receive shift register
RDR: Receive data register
TSR: Transmit shift register
TDR: Transmit data register
SMR: Serial mode register
SCR: Serial control register
SSR: Serial status register
BRR: Bit rate register
SDCR: Serial direction control register
Pφ
Pφ/8
Pφ/32
Pφ/128
TEI
TXI
RXI
ERI
Figure 13.1 Block Diagram of SCI
Rev.4.00 Mar. 27, 2008 Page 394 of 882
REJ09B0108-0400