SH7144_08 Datasheet, PDF (217/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

10. Direct Memory Access Controller (DMAC)
Bit Bit Name Initial Value R/W
Description
17 AM
0
(R/W)*² Acknowledge Mode
In dual address mode, selects whether to output
DACK in the data write cycle or data read cycle. In
single address mode, DACK is always output
irrespective of the setting of this bit. This bit is valid
only for CHCR_0 and CHCR_1. For CHCR_2 and
CHCR_3, this bit is always read as 0 and the write
value should always be 0.
0: Outputs DACK during read cycle
1: Outputs DACK during write cycle
16 AL
0
(R/W)*² Acknowledge Level
Specifies whether to set DACK (acknowledge) signal
output to active high or active low. This bit is valid
only with CHCR_0 and CHCR_1. For CHCR_2 and
CHCR_3, this bit is always read as 0 and the write
value should always be 0.
0: Active high output
1: Active low output
15 DM1
0
14 DM0
0
R/W
Destination Address Mode 1, 0
R/W
These bits specify increment/decrement of the DMA
transfer destination address. These bit specifications
are ignored when transferring data from an external
device to address space in single address mode.
00: Destination address fixed
01: Destination address incremented (+1 during 8-bit
transfer, +2 during 16-bit transfer, +4 during 32-
bit transfer)
10: Destination address decremented (–1 during 8-bit
transfer, –2 during 16-bit transfer, –4 during 32-bit
transfer)
11: Setting prohibited
Rev.4.00 Mar. 27, 2008 Page 173 of 882
REJ09B0108-0400