SH7144_08 Datasheet, PDF (133/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

6. Interrupt Controller (INTC)
6.4.4 H-UDI Interrupt
The user debugging interface (H-UDI) interrupt has a priority level of 15, and occurs when an H-
UDI interrupt instruction is serially input. H-UDI interrupt requests are detected by edge and are
held until accepted. H-UDI exception processing sets the interrupt mask level bits (I3-I0) in the
status register (SR) to level 15. For more details on the H-UDI interrupt, see section 22, User
Debugging Interface (H-UDI).
Rev.4.00 Mar. 27, 2008 Page 89 of 882
REJ09B0108-0400