SH7144_08 Datasheet, PDF (490/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

13. Serial Communication Interface (SCI)
Synchroniza-
tion clock
Serial data
Transfer
direction
Bit 0 Bit 1
Bit 7 Bit 0 Bit 1
Bit 6 Bit 7
TDRE
TEND
TXI interrupt
request
generated
Data written to TDR
and TDRE flag cleared
to 0 in TXI interrupt
processing routine
1 frame
TXI interrupt
request
generated
TEI interrupt
request
generated
Figure 13.16 Sample SCI Transmission Operation in Clocked Synchronous Mode
Initialization
[1]
Start transmission
Read TDRE flag in SSR
[2]
No
TDRE = 1
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
All data transmitted?
Yes
No
[3]
[1] SCI initialization:
Set the TxD pin using the PFC.
[2] SCI status check and transmit data
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR and clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DMAC or
DTC is activated by a transmit data
empty interrupt (TXI) request and data
is written to TDR.
Read TEND flag in SSR
No
TEND = 1
Yes
Clear TE bit in SCR to 0
<End>
Figure 13.17 Sample Serial Transmission Flowchart
Rev.4.00 Mar. 27, 2008 Page 446 of 882
REJ09B0108-0400