SH7144_08 Datasheet, PDF (545/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
14.4.4 Operations in Master Reception
In master receive mode, the master device outputs the receive clock, receives data, and returns
acknowledgements of reception. The slave device transmits the data.
The master device transmits data of the slave address + R/W (1: Read) in the first frame after start
condition issuance in master transmit mode. After the slave device is selected, operation is
changed to reception.
Reception with HNDS Function (HNDS = 1):
Figure 14.10 is a flowchart that gives an example of operations in master receive mode (HNDS =
1).
Rev.4.00 Mar. 27, 2008 Page 501 of 882
REJ09B0108-0400