SH7144_08 Datasheet, PDF (496/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

13. Serial Communication Interface (SCI)
13.7.2 Data Format (Except for Block Transfer Mode)
Figure 13.22 shows the transfer data format in smart card interface mode.
• One frame consists of 8-bit data plus a parity bit in asynchronous mode.
• In transmission, a guard time of at least 2 etu (Elementary time unit: the time for transfer of
one bit) is left between the end of the parity bit and the start of the next frame.
• If a parity error is detected during reception, a low error signal level is output for one etu
period, 10.5 etu after the start bit.
• If an error signal is sampled during transmission, the same data is retransmitted automatically
after a delay of 2 etu or longer.
When there is no parity error
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
Transmitting station output
When a parity error occurs
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
DE
Transmitting station output
[Legend]
DS:
Start bit
D0 to D7: Data bits
Dp:
Parity bit
DE:
Error signal
Receiving station
output
Figure 13.22 Normal Smart Card Interface Data Format
Data transfer with other types of IC cards (direct convention and inverse convention) should be
performed as described in the following.
(Z) A Z Z A Z Z Z A A Z
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(Z) State
Figure 13.23 Direct Convention (DIR = SINV = O/E = 0)
With the direction convention type IC and the above sample start character, the logic 1 level
corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order.
The above start character data is H'3B. For the direct convention type, clear the DIR and SINV
Rev.4.00 Mar. 27, 2008 Page 452 of 882
REJ09B0108-0400