SH7144_08 Datasheet, PDF (115/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

5. Exception Processing
5.5 Exceptions Triggered by Instructions
5.5.1 Types of Exceptions Triggered by Instructions
Exception processing can be triggered by trap instruction, illegal slot instructions, and general
illegal instructions, as shown in table 5.9.
Table 5.9 Types of Exceptions Triggered by Instructions
Type
Trap instruction
Illegal slot
instructions
General illegal
instructions
Source Instruction
TRAPA
Undefined code placed
immediately after a delayed
branch instruction (delay slot) or
instructions that rewrite the PC
Undefined code anywhere
besides in a delay slot
Comment
—
Delayed branch instructions: JMP, JSR,
BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Instructions that rewrite the PC: JMP, JSR,
BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF
—
5.5.2 Trap Instructions
When a TRAPA instruction is executed, trap instruction exception processing starts. The CPU
operates as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the TRAPA instruction.
3. The start address of the exception service routine is fetched from the exception processing
vector table that corresponds to the vector number specified in the TRAPA instruction. That
address is jumped to and the program starts executing. The jump in this case is not a delayed
branch.
Rev.4.00 Mar. 27, 2008 Page 71 of 882
REJ09B0108-0400