SH7144_08 Datasheet, PDF (519/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
Bit Bit Name Initial Value R/W Description
2 BC2
0
R/W Bit Counter
1 BC1
0
0 BC0
0
R/W These bits specify the number of bits to be transferred
R/W ^{in the next transfer. Set the BC2 to BC0 bits in the}
intervals between the transfer of frames. Set the BC2 to
BC0 bits to other than 000 when SCL is low.
The bit counter is initialized to 000 on detection of the
start condition. In addition, this counter returns to 000
on completion of the transfer of all data.
I2C bus format
Synchronous serial format
000: 9 bits
000: 8 bits
001: 2 bits
001: 1 bit
010: 3 bits
010: 2 bits
011: 4 bits
011: 3 bits
100: 5 bits
100: 4 bits
101: 6 bits
101: 5 bits
110: 7 bits
110: 6 bits
111: 8 bits
111: 7 bits
Rev.4.00 Mar. 27, 2008 Page 475 of 882
REJ09B0108-0400