SH7144_08 Datasheet, PDF (903/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

D. I/O Port Block Diagrams
RES
R
Q PE1DR D
C
PEDRL.WR
DRAK0 (DMAC)
TIOC0B (MTU)
PEDRL.RD
TIOC0B (MTU)
AUDMD (AUD)
PFC
Q PE1MD0
Q PE1MD1
Q PE1IOR
AUD module standby
Software standby
SBYCR
Q Hi-Z
RES: Reset signal
PEDRL.RD: Port E data register L read signal
PEDRL.WR: Port E data register L write signal
Figure D.47 PE1/TIOC0B/DRAK0/AUDMD
Pins
PE1/TIOC0B/
DRAK0/
AUDMD
Symbol in Figure D.47
Available Products
SH7144
SH7145
Masked ROM
Masked ROM
version/
version/
F-ZTAT ROM less F-ZTAT ROM less
PE1 TIOC0B DRAK0 AUDMD version _version
version version
PE1 TIOC0B DRAK0 AUDMD ⎯
⎯
(MTU) (DMAC) (AUD)
√
⎯
Rev.4.00 Mar. 27, 2008 Page 859 of 882
REJ09B0108-0400