SH7144_08 Datasheet, PDF (253/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

10. Direct Memory Access Controller (DMAC)
The DMAC internal status, due to the above operation after completion of the fourth transfer, is
indicated in table 10.9 for both address reload on and off.
Table 10.9 DMAC Internal Status
Item
Address Reload On
Address Reload Off
SAR
H'FFFF8428
H'FFFF842C
DAR
H'FFFFF004
H'FFFFF004
DMATCR
H'0000007C
H'0000007C
Bus mastership
Released
Maintained
DMAC operation
Halted
Processing continues
Interrupts
Not issued
Not issued
Transfer request source flag clear Executed
Not executed
Notes: 1. Interrupts are executed until the DMATCR value becomes 0, and if the IE bit of the
CHCR is set to 1, are issued regardless of whether the address reload is on or off.
2. If transfer request source flag clears are executed until the DMATCR value becomes 0,
they are executed regardless of whether the address reload is on or off.
3. Designate burst mode when using the address reload function. There are cases where
abnormal operation will result if it is executed in cycle steal mode.
4. Designate a multiple of four for the DMATCR value when using the address reload
function. There are cases where abnormal operation will result if anything else is
designated.
To execute transfers after the fifth one when the address reload is on, make the transfer request
source issue another transfer request signal.
Rev.4.00 Mar. 27, 2008 Page 209 of 882
REJ09B0108-0400