SH7144_08 Datasheet, PDF (158/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

8. Data Transfer Controller (DTC)
On-chip ROM
On-chip RAM
On-chip
peripheral
module
CPU interrupt request
source clear control
Interrupt request
External
memory
External device
(memory-
mapped)
Register
control
Activation
control
Request
priority
control
Bus interface
DTMR
DTCR
DTSAR
DTDAR
DTIAR
DTER
DTCSR
DTBR
DTC module bus
DTC
Bus controller
[Legend]
DTMR: DTC mode register
DTCR: DTC transfer count register
DTSAR: DTC source address register
DTDAR: DTC destination address register
DTIAR: DTC initial address register
DTER: DTC enable register
DTCSR: DTC control/status register
DTBR: DTC information base register
Figure 8.1 Block Diagram of DTC
Rev.4.00 Mar. 27, 2008 Page 114 of 882
REJ09B0108-0400