SH7144_08 Datasheet, PDF (902/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

D. I/O Port Block Diagrams
RES
R
Q PE0DR D
C
PEDRL.WR
AUDCK (AUD)
TIOC0A (MTU)
PEDRL.RD
TIOC0A (MTU)
DREQ0 (DMAC)
AUDCK (AUD)
PFC
Q PE0MD0
Q PE0MD1
AUDMD
Q PE0IOR
Software standby
AUD module standby
SBYCR
Q Hi-Z
RES: Reset signal
PEDRL.RD: Port E data register L read signal
PEDRL.WR: Port E data register L write signal
Figure D.46 PE0/TIOC0A/DREQ0/AUDCK
Pins
PE0/TIOC0A/
DREQ0/
AUDCK
Symbol in Figure D.46
PE0 TIOC0A DREQ0 AUDCK
PE0 TIOC0A DREQ0 AUDCK
(MTU) (DMAC) (AUD)
Available Products
SH7144
SH7145
Masked ROM
version/
F-ZTAT ROM less
version version
F-ZTAT
version
Masked ROM
version/
ROM less
version
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Rev.4.00 Mar. 27, 2008 Page 858 of 882
REJ09B0108-0400