SH7144_08 Datasheet, PDF (524/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
Bit Bit Name
1 IRIC
Initial Value R/W Description
0
R/(W)* I²C Bus Interface Interrupt Request Flag
The IRIC flag indicates that the I²C bus interface has
generated an interrupt request for the CPU.
The timing with which the IRIC flag is set changes
according to the combination of the values of the FS
bit in SAR, the FSX bit in SARX and the WAIT bit in
ICMR. Refer to section 14.4.7, Timing for Setting IRIC
and the Control of SCL. In addition, the condition on
which the IRIC flag is set changes according to the
setting of the ACKE bit in ICCR.
[Setting conditions]
• I²C bus format in master mode
When the start condition is detected from the bus
line state after the start condition has been set.
(i.e., when the ICDRE flag is set to 1 for
transmission of the first frame).
When WAIT = 1, a wait is inserted between the
data bits and the acknowledge bit.
(i.e., at the falling edge of the 8th transmit/receive
clock)
When the transfer of data has been completed.
(i.e., at the rising edge of the 9th cycle of
transmit/receive clock with no wait inserted)
When a slave address is received after bus conflict
is lost.
(i.e., first frame following start condition)
When the ACKE bit is 1, and 1 is received as an
acknowledge bit.
(i.e., when the ACKB bit is set to 1).
When the AL flag is set to 1 because of a bus
conflict.
Rev.4.00 Mar. 27, 2008 Page 480 of 882
REJ09B0108-0400