SH7144_08 Datasheet, PDF (183/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

9. Bus State Controller (BSC)
9.2 Input/Output Pins
Table 9.1 shows the bus state controller pin configuration.
Table 9.1 Pin Configuration
Name
Abbr.
I/O Description
Address bus
A21 to A0
Output Address output (Address bus A21 to A18 pins are
disabled and I/O port function is enabled after
power-on-reset.)
Data bus
D31 to D0 I/O 32-bit data bus
Chip select
CS0 to CS7* Output Chip select signal indicating the area being
accessed
Read
RD
Output Strobe that indicates the read cycle
Write
WRHH
Output Strobe that indicates a write cycle to the first byte
(D31 to D24)
WRHL
Output Strobe that indicates a write cycle to the second
byte (D23 to D16)
WRH
Output Strobe that indicates a write cycle to the third byte
(D15 to D8)
WRL
Output Strobe that indicates a write cycle to the fourth byte
(D7 to D0)
Wait
WAIT
Input Wait state request signal
Bus request
BREQ
Input Bus request input
Bus acknowledge BACK
Output Bus use enable output
Note: * Pins CS4 to CS7 are available only for the masked ROM version and ROMless version.
Rev.4.00 Mar. 27, 2008 Page 139 of 882
REJ09B0108-0400