SH7144_08 Datasheet, PDF (167/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

8. Data Transfer Controller (DTC)
Register
information
start address
Memory space
DTMR
DTCRA
DTSAR
DTDAR
Memory space
DTMR
DTCRA
DTIAR
DTSAR
DTDAR
Memory space
DTMR
DTCRA
DTCRB
DTSAR
DTDAR
Register
information
Normal mode
Repeat mode Block transfer mode
Figure 8.3 DTC Register Information Allocation in Memory Space
Figure 8.4 shows the correspondence between DTC vector addresses and register information
allocation. For each DTC activating source there are 2 bytes in the DTC vector table, which
contain the register information start address.
Table 8.1 shows the correspondence between activating sources and vector addresses. When
activating with software, the vector address is calculated as H'0400 + DTVEC[7:0].
Through DTC activation, a register information start address is read from the vector table, then
register information placed in memory space is read from that register information start address.
Always designate register information start addresses in multiples of four.
DTBR
Transfer information
start address
(upper 16 bits)
DTC vector table
DTC vector address
Register information
start address
(lower 16 bits)
Memory space
Register
information
Figure 8.4 Correspondence between DTC Vector Address and Transfer Information
Rev.4.00 Mar. 27, 2008 Page 123 of 882
REJ09B0108-0400