SH7144_08 Datasheet, PDF (32/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

Figure 13.22 Normal Smart Card Interface Data Format ........................................................... 452
Figure 13.23 Direct Convention (DIR = SINV = O/E = 0)......................................................... 452
Figure 13.24 Inverse Convention (DIR = SINV = O/E = 1)....................................................... 453
Figure 13.25 Receive Data Sampling Timing in Smart Card Interface Mode
(Using Clock of 372 Times Bit Rate).................................................................... 454
Figure 13.26 Retransfer Operation in SCI Transmit Mode......................................................... 457
Figure 13.27 TEND Flag Generation Timing in Transmit Operation......................................... 457
Figure 13.28 Example of Transmit Processing Flow.................................................................. 458
Figure 13.29 Timing for Fixing Clock Output Level.................................................................. 459
Figure 13.30 Example of Clocked Synchronous Transmission with DMAC/DTC .................... 464
Section 14 I²C Bus Interface (IIC) Option
Figure 14.1 A Block Diagram of the I²C Bus Interface .............................................................. 469
Figure 14.2 Example of the Connection of I²C Bus Interfaces
(This LSI Is the Master Device).............................................................................. 470
Figure 14.3 I²C Bus Data Format (I²C Bus Format) ................................................................... 493
Figure 14.4 I²C Bus Data Format (Serial Format) ...................................................................... 493
Figure 14.5 I²C Bus Timing ........................................................................................................ 494
Figure 14.6 An Example of IIC Initialization Flowchart............................................................ 495
Figure 14.7 Example: Flowchart of Operations in the Master Transmit Mode .......................... 497
Figure 14.8 An Example of the Timing of Operations in Master Transmit Mode
(MLS = WAIT = 0) ................................................................................................. 499
Figure 14.9 An Example of the Stop Condition Issuance Timing in Master Transmit Mode
(MLS = WAIT = 0) ................................................................................................. 500
Figure 14.10 Example: Flowchart of Operations in the Master Receive Mode (HNDS = 1) ..... 502
Figure 14.11 An Example of the Timing of Operations in Master Receive Mode
(MLS = WAIT = 0, HNDS = 1) ............................................................................ 504
Figure 14.12 An Example of the Stop Condition Issuance Timing in Master Receive Mode
(MLS = WAIT = 0, HNDS = 1) ............................................................................ 504
Figure 14.13 Example: Flowchart of Operations in Master Receive Mode
(Multiple Bytes Reception) (WAIT = 1) ............................................................... 505
Figure 14.14 Example: Flowchart of Operations in Master Receive Mode
(One Byte Reception) (WAIT = 1)........................................................................ 506
Figure 14.15 An Example of the Timing of Operations in Master Receive Mode
(MLS = ACKB = 0, WAIT = 1) ............................................................................ 508
Figure 14.16 An Example of the Stop Condition Issuance Timing in Master Receive Mode
(MLS = ACKB = 0, WAIT = 1) ............................................................................ 509
Figure 14.17 Example: Flowchart of Operations in the Slave Receive Mode (HNDS = 1) ....... 510
Figure 14.18 An Example of the Timing of Operations in Slave Receive Mode 1
(MLS = 0, HNDS = 1)........................................................................................... 512
Rev.4.00 Mar. 27, 2008 Page xxxii of xliv
REJ09B0108-0400