SH7144_08 Datasheet, PDF (430/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

12. Watchdog Timer
TCNT value
H'FF
Overflow
H'00
WT/IT = 1 H’00 written
TME = 1 in TCNT
Time
WOVF = 1 WT/IT = 1 H’00 written
TME = 1 in TCNT
WDTOVF and internal
reset generated
WDTOVF
signal
Internal reset
signal*
WT/IT: Timer mode select bit
TME: Timer enable bit
128 φ clocks
512 φ clocks
Note: * Internal reset signal occurs only when the RSTE bit is set to 1.
Figure 12.2 Operation in Watchdog Timer Mode
12.4.2 Interval Timer Mode
To use the WDT as an interval timer, clear WT/IT to 0 and set TME to 1 in TCSR. An interval
timer interrupt (ITI) is generated each time the timer counter (TCNT) overflows. This function can
be used to generate interval timer interrupts at regular intervals.
TCNT value
H'FF
Overflow
Overflow
Overflow Overflow
H'00
WT/IT = 0
ITI
TME = 1
ITI
ITI
Time
ITI
ITI: Interval timer interrupt request generation
Figure 12.3 Operation in Interval Timer Mode
Rev.4.00 Mar. 27, 2008 Page 386 of 882
REJ09B0108-0400