SH7144_08 Datasheet, PDF (214/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

10. Direct Memory Access Controller (DMAC)
10.3 Register Descriptions
The DMAC has the following registers. The DMAC has a total of 17 registers. Each channel has
four control registers. One other control register is shared by all channels. For register address and
their states in each operating mode, refer to section 25, List of Registers.
• DMA source address register_0 (SAR_0)
• DMA destination address register_0 (DAR_0)
• DMA transfer count register_0 (DMATCR_0)
• DMA channel control register_0 (CHCR_0)
• DMA source address register_1 (SAR_1)
• DMA destination address register_1 (DAR_1)
• DMA transfer count register_1 (DMATCR_1)
• DMA channel control register_1 (CHCR_1)
• DMA source address register_2 (SAR_2)
• DMA destination address register_2 (DAR_2)
• DMA transfer count register_2 (DMATCR_2)
• DMA channel control register_2 (CHCR_2)
• DMA source address register_3 (SAR_3)
• DMA destination address register_3 (DAR_3)
• DMA transfer count register_3 (DMATCR_3)
• DMA channel control register_3 (CHCR_3)
• DMA operation register (DMAOR)
10.3.1 DMA Source Address Registers_0 to 3 (SAR_0 to SAR_3)
DMA source address registers_0 to 3 (SAR_0 to SAR_3) are 32-bit readable/writable registers
that specify the source address of a DMA transfer. These registers have a count function, and
during a DMA transfer, they indicate the next source address. In single-address mode, SAR values
are ignored when a device with DACK has been specified as the transfer source.
Specify a 16-bit or 32-bit boundary address when doing 16-bit or 32-bit data transfers. Operation
cannot be guaranteed on any other addresses.
When this register is accessed in 16 bits, the value of another 16 bits that are not accessed is
retained.
The initial value of SAR is undefined.
Rev.4.00 Mar. 27, 2008 Page 170 of 882
REJ09B0108-0400