SH7144_08 Datasheet, PDF (193/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

9. Bus State Controller (BSC)
Bit Bit Name Initial Value R/W Description
7
CW3
1
R/W Idle cycles at continuous access to CS3 and CS7 spaces
This bit inserts an idle cycle and negates the CS3 signal to
make the bus cycle end obvious when accessing the CS3
space continuously. An idle cycle set by this bit is also
inserted when access is made to the CS7 space after
access to the CS3 space. In addition, an idle cycle set by
this bit is inserted when continuous access is made to the
CS7 space, and when access is made to the CS3 space
after access to the CS7 space.
0: No idle cycle inserted at continuous access to the CS3
and CS7 spaces.
1: One idle cycle inserted at continuous access to the CS3
and CS7 spaces.
When the write cycle follows the read cycle, the larger of
the value specified with IW and that specified with CW is
used as the idle cycles to be inserted.
6
CW2
1
R/W Idle cycles at continuous access to CS2 and CS6 spaces
This bit inserts an idle cycle and negates the CS2 signal to
make the bus cycle end obvious when accessing the CS2
space continuously. An idle cycle set by this bit is also
inserted when access is made to the CS6 space after
access to the CS2 space. In addition, an idle cycle set by
this bit is inserted when continuous access is made to the
CS6 space, and when access is made to the CS2 space
after access to the CS6 space.
0: No idle cycle inserted at continuous access to the CS2
and CS6 spaces.
1: One idle cycle inserted at continuous access to the CS2
and CS6 spaces.
When the write cycle follows the read cycle, the larger of
the value specified with IW and that specified with CW is
used as the idle cycles to be inserted.
Rev.4.00 Mar. 27, 2008 Page 149 of 882
REJ09B0108-0400