SH7144_08 Datasheet, PDF (565/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
14.4.7 Timing for Setting IRIC and the Control of SCL
The timing with which the interrupt-request flag (IRIC) is set varies according to the settings of
the WAIT bit in ICMR, FS bit in SAR, and the FSX bit in SARX. When the ICDRE and ICDRF
flags are set to 1, the level on SCL is automatically set low in synchronization with the internal
clock after the transfer of one frame of data. Figures 14.25 to 14.27 show the timing with which
IRIC is set and the control of SCL.
When WAIT = 0, and FS = 0 or FSX = 0 (I²C bus format, no wait)
SCL
7
8
9
1
2
3
SDA
7
8
A
1
2
3
IRIC
User processing
IRIC clear
(a) When data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception.
SCL
7
8
9
1
SDA
7
8
A
1
IRIC
User processing
IRIC clear
ICDR write (during transmission)
or ICDR read (during reception)
IRIC clear
(b) When data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception
Figure 14.25 IRIC Flag Set Timing and the Control of SCL (1)
Rev.4.00 Mar. 27, 2008 Page 521 of 882
REJ09B0108-0400