SH7144_08 Datasheet, PDF (818/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

26. Electrical Characteristics
26.3.3 Control Signal Timing
Table 26.5 shows control signal timing.
Table 26.5 Control Signal Timing
Conditions: V_CC = PLLV_CC =3.3 V ± 0.3 V, AV_CC = 3.3 V ± 0.3 V, AV_CC = V_CC ± 0.3 V,
AV_ref = 3.0 V to AV_CC , V_SS = PLLV_SS = AV_SS = 0 V, T_a = –20°C to +75°C
(regular specifications), T_a = –40°C to +85°C (wide-range specifications),
When programming or erasing flash memory, T_a = –20°C to +75°C.
Item
RES rise time, fall time
RES pulse width
RES setup time
MRES pulse width
MRES setup time
MD3 to MD0 setup time
NMI rise time, fall time
NMI setup time
NMI hold time
IRQ7 to IRQ0 setup time* (edge detection)
IRQ7 to IRQ0 setup time* (level detection)
IRQ7 to IRQ0 hold time
IRQOUT output delay time
Bus request setup time
Bus acknowledge delay time 1
Bus acknowledge delay time 2
Bus three-state delay time
Symbol
t ,t
RESr RESf
t_RESW
t_RESS
t_MRESW
t_MRESS
t_MDS
t ,t
NMIr NMIf
t
NMIS
t
NMIH
t
IRQES
t_IRQLS
t_IRQEH
t_IRQOD
t_BRQS
t_BACKD1
t
BACKD2
t
BZD
Min.
⎯
25
35
20
35
20
⎯
35
35
19
19
19
⎯
19
⎯
⎯
⎯
Max.
200
⎯
⎯
⎯
⎯
⎯
200
⎯
⎯
⎯
⎯
⎯
100
⎯
35
35
35
Unit
ns
t_cyc
ns
t_cyc
ns
t_cyc
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure
Figure 26.5
Figure 26.6
Figure 26.7
Figure 26.8
[Operating Precautions]
* The RES, MRES, NMI and IRQ7 to IRQ0 signals are asynchronous inputs, but when the setup
times shown here are observed, the signals are considered to have been changed at clock rise
(RES, MRES) or fall (NMI and IRQ7 to IRQ0). If the setup times are not observed, the
recognition of these signals may be delayed until the next clock rise or fall.
Rev.4.00 Mar. 27, 2008 Page 774 of 882
REJ09B0108-0400