SH7144_08 Datasheet, PDF (880/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

D. I/O Port Block Diagrams
AUDATAm (AUD)
Dn (BSC)
RES
R
Q PDnDR D
C
PDDRL.WR
PDDRL.RD
Din
AUDATAm (AUD)
PFC
Q PDnMD0
Q PDnMD1
Dout
Q PDnIOR
AUDSYNC
AUD reset
AUDMD
SBYCR
Q Hi-Z
Bus release
Software standby
AUD module standby
RES: Reset signal
PDDRL.RD: Port D data register L read signal
PDDRL.WR: Port D data register L write signal
Din: Data input timing signal
Dout: Data output timing signal
Figure D.24 PDn/Dn/AUDATAm
Symbol in Figure D.24
Pins
PDn Dn
PD8/D8/ PD8 D8
AUDATA0
(BSC)
PD9/D9/ PD9 D9
AUDATA1
(BSC)
PD10/D10/ PD10 D10
AUDATA2
(BSC)
PD11/D11/ PD11 D11
AUDATA3
(BSC)
AUDATAm
AUDATA0
(AUD)
AUDATA1
(AUD)
AUDATA2
(AUD)
AUDATA3
(AUD)
Available Products
SH7144
SH7145
F-ZTAT
version
Masked ROM
version/
ROM less F-ZTAT
version
version
Masked ROM
version/
ROM less
version
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Rev.4.00 Mar. 27, 2008 Page 836 of 882
REJ09B0108-0400