SH7144_08 Datasheet, PDF (500/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

13. Serial Communication Interface (SCI)
13.7.6 Serial Data Transmission (Except for Block Transfer Mode)
As data transmission in smart card interface mode involves error signal sampling and
retransmission processing, the operations are different from those in normal serial communication
interface mode (except for block transfer mode). Figure 13.26 illustrates the retransfer operation
when the SCI is in transmit mode.
1. If an error signal is sampled from the receiving end after transmission of one frame is
completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is set at this time, an ERI
interrupt request is generated. The ERS bit in SSR should be cleared to 0 by the time the next
parity bit is sampled.
2. The TEND flag in SSR is not set for a frame in which an error signal is received. Data is
retransferred from TDR to TSR, and retransmitted automatically.
3. If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.
Transmission of one frame, including a retransfer, is decided to have been completed, and the
TEND flag in SSR is set to 1. If the TIE bit in SCR is set at this time, a TXI interrupt request is
generated. Writing transmit data to TDR transmits the next data.
Figure 13.28 shows an example of a flowchart for transmission.
A sequence of transmit operations can be performed automatically by specifying the DMAC or
DTC to be activated with a TXI interrupt source.
In a transmit operation, the TDRE flag is set to 1 at the same time as the TEND flag in SSR is set,
and a TXI interrupt request will be generated if the TIE bit in SCR has been set to 1.
If the TXI request is designated beforehand as a DMAC or DTC activation source, the DMAC or
DTC will be activated by the TXI request, and transfer of the transmit data will be carried out. The
TDRE and TEND flags are automatically cleared to 0 when data is transferred by the DMAC or
DTC.
In the event of an error, the SCI retransmits the same data automatically. During this period, the
TEND flag remains cleared to 0 and the DMAC or DTC is not activated. Therefore, the SCI and
DMAC or DTC will automatically transmit the specified number of bytes in the event of an error,
including retransmission. However, the ERS flag is not cleared automatically when an error
occurs, and so the RIE bit should be set to 1 beforehand so that an ERI interrupt request will be
generated in the event of an error, and the ERS flag will be cleared.
When performing transfer using the DMAC or DTC, it is essential to set and enable the DMAC or
DTC before carrying out SCI setting.
Rev.4.00 Mar. 27, 2008 Page 456 of 882
REJ09B0108-0400