SH7144_08 Datasheet, PDF (460/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

13. Serial Communication Interface (SCI)
13.3.9 Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 13.2 shows
the relationships between the N setting in BRR and the effective bit rate B₀ for asynchronous,
clocked synchronous, and smart card interface modes. The initial value of BRR is H'FF, and it can
be read from or written to by the CPU at all times.
Table 13.2 Relationships between N Setting in BRR and Effective Bit Rate B₀
Mode
Asynchronous mode
(n = 0)
Asynchronous mode
(n = 1 to 3)
Clocked synchronous
mode (n = 0)
Bit Rate
Pφ × 10⁶
B₀ = _{32 × 22n × (N + 1)}
Pφ × 10⁶
B₀ = _{32 × 22n+1 × (N + 1)}
Pφ × 10⁶
B₀ = _{4 × 22n × (N + 1)}
Error
Error (%) =
B₀
B₁
– 1^⎞⎠ × 100
Error (%) =
B₀
B₁
– 1^⎞⎠ × 100
—
Clocked synchronous
Pφ × 10⁶
mode (n = 1 to 3)
B₀ = _{4 × 22n+1 × (N + 1)}
—
Smaet card interface
mode (n = 0)
Smaet card interface
mode (n = 1 to 3)
Pφ × 10⁶
B₀ = _{S × 22n+1 × (N + 1)}
Pφ × 10⁶
B₀ = _{S × 22n+2 × (N + 1)}
Error (%) =
B₀
B₁
– 1^⎞⎠ × 100
Error (%) =
B₀
B₁
– 1^⎞⎠ × 100
[Legend]
B₀: Effective bit rate (bit/s) Actual transfer speed according to the register settings
B : Logical bit rate (bit/s) Specified transfer speed of the target system
1
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
Pφ: Peripheral clock operating frequency (MHz)
n and S: Determined by the SMR settings shown in the following tables.
Rev.4.00 Mar. 27, 2008 Page 416 of 882
REJ09B0108-0400