SH7144_08 Datasheet, PDF (251/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

10. Direct Memory Access Controller (DMAC)
10.5.2 Example of DMA Transfer between External RAM and External Device with
DACK
Below is an transfer example in which the transfer source is an external memory and the transfer
destination is an external device with DACK, using channel 1 of the DMAC which requires an
external request in single address mode.
Table 10.7 indicates the transfer conditions and the setting values of each of the registers.
Table 10.7 Transfer Conditions and Register Set Values for Transfer between External
RAM and External Device with DACK
Transfer Conditions
Register
Transfer source: external RAM
SAR_1
Transfer destination: external device with DACK DAR_1
Transfer count: 32 times
DMATCR_1
Transfer source address: decremented
CHCR_1
Transfer destination address: (setting ineffective)
Transfer request source: external pin (DREQ1) edge
detection
Bus mode: burst
Transfer unit: word
No interrupt request generation at end of transfer
Channel priority ranking: 2 > 0 > 1 > 3
DMAOR
Value
H'00400000
(access by DACK)
H'00000020
H'00002269
H'0201
Rev.4.00 Mar. 27, 2008 Page 207 of 882
REJ09B0108-0400