SH7144_08 Datasheet, PDF (54/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

1. Overview
Type
Bus control
Direct
memory
access
controller
(DMAC)
Symbol
I/O
CS3 to CS0 Output
CS5, CS4 Output
(SH7145
masked ROM
version and
ROM less
version only)
CS7, CS6 Output
(masked
ROM version
and ROM
less version
only)
RD
Output
WRHH
Output
(SH7145
only)
WRHL
Output
(SH7145
only)
WRH
Output
WRL
Output
WAIT
Input
DREQ0,
DREQ1
DRAK0,
DRAK1
Input
Output
DACK0,
DACK1
Output
Name
Chip select
3 to 0
Chip select
5, 4
Function
Chip select signal for external memory or
devices.
Chip select
7, 6
Read
Write HH
Shows reading from external devices.
Shows writing into the HH 8 bits (bits 31 to
24) of the external data.
Write HL
Shows writing into the HL 8 bits (bits 23 to
16) of the external data.
Write
upper half
Shows writing into the upper 8 bits (bits 15
to 8) of the external data.
Write lower
half
Shows writing into the lower 8 bits (bit7 to
bit0) of the external data.
Wait
Inserts the wait cycles into the bus cycle
when accessing the external spaces.
DMA transfer DMA request input pins from an external
request
device.
DREQ request Outputs an acknowledge signal to the
acknowledge external device that has input a DMA
transfer request signal.
DMA transfer Outputs a strobe to the I/O of the external
strobe
device that has input a DMA transfer
request signal.
Rev.4.00 Mar. 27, 2008 Page 10 of 882
REJ09B0108-0400