SH7144_08 Datasheet, PDF (245/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

10. Direct Memory Access Controller (DMAC)
Note: With cycle steal and single address operation, sampling timing is the same regardless of
whether DREQ detection is by level or by edge.
CK
DREQ
DRAK
Bus
cycle
DACK
CPU
CPU
CPU DMAC(R) DMAC(W) DMAC(R) DMAC(W) DMAC(R) DMAC(W) CPU DMAC(R)
Figure 10.18 Burst Mode, Dual Address and Level Detection (Fastest Operation)
CK
DREQ
DRAK
Bus
cycle
DACK
CPU
CPU
CPU
DMAC(R)
DMAC(W)
DMAC(R) DMAC(W)
DMAC(R)
Figure 10.19 Burst Mode, Dual Address and Level Detection (Normal Operation)
1st sampling
2nd sampling
CK
DREQ
DRAK
Bus
cycle
CPU(1)
CPU(2) CPU(3) Dummy
DACK
3rd sampling
DMAC
4th sampling
DMAC
DMAC
CPU(4) Dummy
Figure 10.20 Burst Mode, Single Address and Level Detection (Fastest Operation)
Rev.4.00 Mar. 27, 2008 Page 201 of 882
REJ09B0108-0400