SH7144_08 Datasheet, PDF (40/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

Section 8 Data Transfer Controller (DTC)
Table 8.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTEs ................. 124
Table 8.2 Normal Mode Register Functions ......................................................................... 127
Table 8.3 Repeat Mode Register Functions .......................................................................... 128
Table 8.4 Block Transfer Mode Register Functions ............................................................. 129
Table 8.5 Execution State of DTC ........................................................................................ 133
Table 8.6 State Counts Needed for Execution State ............................................................. 133
Section 9 Bus State Controller (BSC)
Table 9.1 Pin Configuration.................................................................................................. 139
Table 9.2 Address Map ......................................................................................................... 142
Table 9.3 Access to On-chip Peripheral I/O Registers.......................................................... 166
Section 10 Direct Memory Access Controller (DMAC)
Table 10.1 DMAC Pin Configuration..................................................................................... 169
Table 10.2 Selecting External Request Modes with RS Bits .................................................. 182
Table 10.3 Selecting On-Chip Peripheral Module Request Modes with RS Bits ................... 183
Table 10.4 Supported DMA Transfers.................................................................................... 187
Table 10.5 Relationship of Request Modes and Bus Modes by DMA Transfer Category ..... 196
Table 10.6 Transfer Conditions and Register Set Values for Transfer
between On-chip SCI and External Memory ........................................................ 206
Table 10.7 Transfer Conditions and Register Set Values for Transfer
between External RAM and External Device with DACK................................... 207
Table 10.8 Transfer Conditions and Register Set Values for Transfer
between A/D Converter (A/D1) and On-chip Memory ........................................ 208
Table 10.9 DMAC Internal Status .......................................................................................... 209
Table 10.10 Transfer Conditions and Register Set Values for Transfer
between External Memory and SCI1 Transmit Side............................................. 210
Section 11 Multi-Function Timer Pulse Unit (MTU)
Table 11.1 MTU Functions..................................................................................................... 214
Table 11.2 Pin Configuration.................................................................................................. 217
Table 11.3 CCLR0 to CCLR2 (Channels 0, 3, and 4) ............................................................ 221
Table 11.4 CCLR0 to CCLR2 (Channels 1 and 2) ................................................................. 221
Table 11.5 TPSC0 to TPSC2 (Channel 0) .............................................................................. 222
Table 11.6 TPSC0 to TPSC2 (Channel 1) .............................................................................. 222
Table 11.7 TPSC0 to TPSC2 (Channel 2) .............................................................................. 223
Table 11.8 TPSC0 to TPSC2 (Channels 3 and 4) ................................................................... 223
Table 11.9 MD0 to MD3 ........................................................................................................ 225
Table 11.10 TIORH_0 (Channel 0) .......................................................................................... 228
Table 11.11 TIORL_0 (Channel 0)........................................................................................... 229
Table 11.12 TIOR_1 (Channel 1) ............................................................................................. 230
Rev.4.00 Mar. 27, 2008 Page xl of xliv
REJ09B0108-0400