SH7144_08 Datasheet, PDF (172/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

8. Data Transfer Controller (DTC)
Table 8.3 Repeat Mode Register Functions
Register
DTMR
DTCRAH
DTCRAL
DTIAR
DTSAR
DTDAR
Values Written Back upon Transfer Information Write
Function
When DTCRA is other than 1 When DTCRA is 1
Operation mode
control
DTMR
DTMR
Transfer count save DTCRAH
DTCRAH
Transfer count
DTCRAL – 1
DTCRAH
Initial address
(Not written back)
(Not written back)
Transfer source
address
Increment/decrement/fixed
(DTS = 0) Increment/
decrement/fixed
(DTS = 1) DTIAR
Transfer destination Increment/decrement/fixed
address
(DTS = 0) DTIAR
(DTS = 1) Increment/
decrement/fixed
DTSAR
or
DTDAR
Repeat area
Transfer
DTDAR
or
DTSAR
Figure 8.7 Memory Mapping in Repeat Mode
Rev.4.00 Mar. 27, 2008 Page 128 of 882
REJ09B0108-0400