SH7144_08 Datasheet, PDF (534/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
14.3.7 Serial Control Register X (SCRX)
SCRX enables or disables I²C bus interface interrupts and confirms the state of reception and
transmission.
Bit Bit Name Initial Value R/W
7, 6 ⎯
All 0
R
5 IICX
0
R/W
4 IICE
0
R/W
3 HNDS
0
R/W
2⎯
0
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
I²C Transfer Rate Select
Along with bits CKS2 to CKS0 in the I²C bus mode
register (ICMR), this bit selects the transfer rate in the
master mode. For details on setting the transfer rate,
see table 14.3.
I²C master Enable
This bit controls access by the CPU to the I²C bus
interface registers (ICCR, ICSR, ICDR/SARX, and
ICMR/SAR) of the I²C bus interface.
0: Disables CPU access to the registers of the I²C bus
interface.
1: Enables CPU access to the registers of the I²C bus
interface.
Hand-Shake Receive Select
This bit enables/disables continuous reception in
receive mode.
When the HNDS bit is cleared to 0, receive operation
is performed continuously after data has been received
successfully while ICDRF flag is 0.
When the HNDS bit is set to 1, SCL is fixed to the low
level thus disabling the next data to be transferred.
The bus line is released and next frame receive
operation is enabled by reading the receive data in
ICDR.
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev.4.00 Mar. 27, 2008 Page 490 of 882
REJ09B0108-0400