SH7144_08 Datasheet, PDF (546/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
Master receive mode
Set TRS = 0 (ICCR)
Set ACKB = 0 (ICSR)
Set HNDS = 1 (SCRX)
Clear the IRIC flag in ICCR
Final reception? ^Yes
No
Read ICDR
Read the IRIC flag in ICCR
No
IRIC = 1?
Yes
Clear the IRIC flag in ICCR
[1] Set receive mode
[2] Dummy read for starting reception (first read)
[5] Read the receive data (second and subsequent read)
[3] Wait for 1 byte of data to be received.
(Set IRIC at the rising edge of the 9th cycle of the
clock for the receive frame.)
[4] Clear IRIC flag.
Set ACKB = 1 (ICSR)
Read ICDR
Read the IRIC flag in ICCR
No
IRIC = 1?
Yes
Clear the IRIC flag in ICCR
Set TRS = 1 (ICCR)
Read ICDR
Write 0 to BBSY and SCP
(ICCR)
End
[6] Set acknowledge data for the final reception.
[7] Read the receive data. Dummy read for starting
reception when the first frame is the final receive data.
[8] Wait for 1 byte of data to be received.
[9] Clear IRIC flag
[10] Read the receive data.
[11] Set stop condition issuance. Generate stop condition.
Figure 14.10 Example: Flowchart of Operations in the Master Receive Mode (HNDS = 1)
Rev.4.00 Mar. 27, 2008 Page 502 of 882
REJ09B0108-0400