SH7144_08 Datasheet, PDF (592/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

15. A/D Converter
Bit Bit Name Initial Value R/W
2 to 0 —
All 1
R
Description
Reserved
These bits are always read as 1. The write value
should always be 1.
15.3.4 A/D Trigger Select Register (ADTSR)
The ADTSR enables an A/D conversion started by an external trigger signal.
Bit Bit Name Initial Value R/W
7 to 4 —
All 0
R
3 TRG1S1 0
R/W
2 TRG1S0 0
R/W
1 TRG0S1 0
R/W
0 TRG0S0 0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
AD Trigger 1 Select 1 and 0
Enable the start of A/D conversion by A/D1 with a
trigger signal.
00: A/D conversion start by external trigger pin
(ADTRG) or MTU trigger is enabled
01: A/D conversion start by external trigger pin
(ADTRG) is enabled
10: A/D conversion start by MTU trigger is enabled
11: Setting prohibited
When changing the operating mode, first clear the
ADST and TRGE bit in the A/D control registers
(ADCR) to 0.
AD Trigger 0 Select 1 and 0
Enable the start of A/D conversion by A/D0 with a
trigger signal.
00: A/D conversion start by external trigger pin
(ADTRG) or MTU trigger is enabled
01: A/D conversion start by external trigger pin
(ADTRG) is enabled
10: A/D conversion start by MTU trigger is enabled
11: Setting prohibited
When changing the operating mode, first clear the
ADST and TRGE bit in the A/D control registers
(ADCR) to 0.
Rev.4.00 Mar. 27, 2008 Page 548 of 882
REJ09B0108-0400