SH7144_08 Datasheet, PDF (370/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

11. Multi-Function Timer Pulse Unit (MTU)
Pφ
Address
Write signal
Compare match
signal
Compare match
buffer signal
Buffer register
TGR write cycle
T1
T2
Buffer register
address
Buffer register write data
N
M
TGR
N
Figure 11.75 Contention between Buffer Register Write and Compare Match
(Channels 3 and 4)
11.7.8 Contention between TGR Read and Input Capture
If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will
be that in the buffer after input capture transfer.
Figure 11.76 shows the timing in this case.
TGR read cycle
T1 T2
Pφ
Address
TGR address
Read signal
Input capture
signal
TGR
Internal data
bus
X
M
M
Figure 11.76 Contention between TGR Read and Input Capture
Rev.4.00 Mar. 27, 2008 Page 326 of 882
REJ09B0108-0400