SH7144_08 Datasheet, PDF (161/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

8. Data Transfer Controller (DTC)
Bit Bit Name Initial Value R/W
7 DTS
Undefined —
6 CHNE
Undefined —
5 DISEL
Undefined —
4 NMIM
Undefined —
3 to 0 —
Undefined —
[Legend]
x:
Don’t care
Description
DTC Transfer Mode Select
Specifies whether the source or the destination is set
to be a repeat area or block area, in repeat mode or
block transfer mode.
0: Destination is repeat area or block area
1: Source is repeat area or block area
DTC Chain Transfer Enable
When this bit is set to 1, a chain transfer will be
performed.
0: Chain transfer is canceled
1: Chain transfer is set
In data transfer with CHNE set to 1, determination of
the end of the specified number of transfers, clearing
of the activation source flag, and clearing of DTER is
not performed.
DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time a data transfer ends. When this
bit is set to 0, a CPU interrupt request is generated at
the time when the specified number of data transfer
ends.
DTC NMI Mode
This bit designates whether to terminate transfers
when an NMI is input during DTC transfers.
0: Terminate DTC transfer upon an NMI
1: Continue DTC transfer until end of transfer being
executed
Reserved
These bits have no effect on DTC operation. The
write value should always be 0.
Rev.4.00 Mar. 27, 2008 Page 117 of 882
REJ09B0108-0400