SH7144_08 Datasheet, PDF (145/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

7. User Break Controller (UBC)
Section 7 User Break Controller (UBC)
The user break controller (UBC) provides functions that make program debugging easier. By
setting break conditions in the UBC, a user break interrupt is generated according to the contents
of the bus cycle generated by the CPU or DMAC/DTC. This function makes it easy to design an
effective self-monitoring debugger, and customers of the chip can easily debug their programs
without using a large in-circuit emulator.
7.1 Features
• There are 5 types of break compare conditions as follows:
⎯ Address
⎯ CPU cycle or DMAC/DTC cycle
⎯ Instruction fetch or data access
⎯ Read or write
⎯ Operand size: longword/word/byte
• User break interrupt generated upon satisfying break conditions
• User break interrupt generated before an instruction is executed by selecting break in the CPU
instruction fetch.
• Module standby mode can be set
UBC0001A_000020010800
Rev.4.00 Mar. 27, 2008 Page 101 of 882
REJ09B0108-0400