SH7144_08 Datasheet, PDF (549/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

14. I²C Bus Interface (IIC) Option
Master receive mode
Set TRS = 0 (ICCR)
Set ACKB = 0 (ICSR)
Set HNDS = 0 (SCRX)
Clear the IRIC flag in ICCR
Set WAIT = 1 (ICMR)
Read ICDR
Read the IRIC flag in ICCR
No
IRIC = 1?
Yes
No
IRTR = 1?
Yes
Final reception? ^Yes
No
Read ICDR
Clear the IRIC flag in ICCR
[1] Set receive mode.
[2] Start receiving. Dummy read.
[3] Wait for a receive wait
(set IRIC at the falling edge of the 8th cycle)
or,
wait for 1 byte to be received
(set IRIC at the rising edge of the 9th cycle).
[4] Determine the end of data reception.
[5] Read the receive data.
[6] Clear the IRIC flag (to cancel wait).
Set ACKB = 1 (ICSR)
Wait for 1 cycle
Set TRS = 1 (ICCR)
Read ICDR
Clear the IRIC flag in ICCR
Read the IRIC flag in ICCR
No
IRIC = 1?
Yes
IRTR = 1?
Yes
No
Clear the IRIC flag in ICCR
[7] Set acknowledge data for the final reception.
[8] Wait for TRS setting.
[9] Set TRS for stop condition issuance.
[10] Read the receive data.
[11] Clear the IRIC flag (to cancel wait).
[12] Wait for a receive wait
(set IRIC at the falling edge of the 8th cycle)
or,
wait for 1 byte to be received
(set IRIC at the rising edge of the 9th cycle).
[13] Determine the end of data reception.
[14] Clear the IRIC flag (to cancel wait).
Set WAIT = 0 (ICMR)
Clear the IRIC flag in ICCR
Read ICDR
Write 0 to BBSY and SCP
(ICCR)
End
[15] Cancel wait mode. Clear the IRIC flag.
(IRIC should be cleared to 0 after setting WAIT = 0)
[16] Read final receive data.
[17] Issue stop condition.
Figure 14.13 Example: Flowchart of Operations in Master Receive Mode
(Multiple Bytes Reception) (WAIT = 1)
Rev.4.00 Mar. 27, 2008 Page 505 of 882
REJ09B0108-0400