SH7144_08 Datasheet, PDF (710/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

19. Flash Memory (F-ZTAT Version)
Bit Bit Name Initial Value R/W Description
3 EV
0
R/W Erase-Verify
When this bit is set to 1 while the FEW and SWE bits
are 1, the flash memory changes to erase-verify
mode. When it is cleared to 0, erase-verify mode is
cancelled.
2 PV
0
R/W Program-Verify
When this bit is set to 1 while the FEW and SWE bits
are 1, the flash memory changes to program-verify
mode. When it is cleared to 0, program-verify mode is
cancelled.
1E
0
R/W Erase
When this bit is set to 1 while the FEW, SWE and
ESU bits are 1, the flash memory changes to erase
mode. When it is cleared to 0, erase mode is
cancelled.
0P
0
R/W Program
When this bit is set to 1 while the FEW, SWE and
PSU bits are 1, the flash memory changes to
program mode. When it is cleared to 0, program
mode is cancelled.
Note: * The value of this bit is 1 when using E10A (when DBGMD is high).
19.5.2 Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is a register that displays the state of flash memory programming/erasing.
Bit Bit Name Initial Value R/W
7 FLER
0
R
6 to 0 —
All 0
R
Description
Indicates that an error has occurred during an
operation on flash memory (programming or erasing).
When FLER is set to 1, flash memory goes to the
error-protection state.
See section 19.9.3, Error Protection, for details.
Reserved
These bits are always read as 0.
Rev.4.00 Mar. 27, 2008 Page 666 of 882
REJ09B0108-0400