SH7144_08 Datasheet, PDF (823/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

26. Electrical Characteristics
V_OH
CK
t_AD
A21 to A0
T1
V_OL
CSn
t_CSD1
RD
(read)
t_RSD1
t_ASR
D31 to D0
(read)
WRx
(write)
D31 to D0
(write)
DACKn
t_WSD1
t_ASW
t_WDD
t_DACKD
T_W
t_OE
t_ACC
T₂
t_CSD2
t_RDS
t_RSD2
t_RDH
t_{WSD2 tWR}
t_WRH
t_WDH
t_DACKD
Note: t_RDH is specified from the negate timing of A21 to A0, CSn, or RD, whichever is first.
Figure 26.10 Basic Cycle (One Software Wait)
Rev.4.00 Mar. 27, 2008 Page 779 of 882
REJ09B0108-0400