SH7144_08 Datasheet, PDF (748/930 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family/SH7144 Series

22. User Debugging Interface (H-UDI)
22.5 Usage Notes
• The registers are not initialized in software standby mode. If TRST is set to 0 in software
standby mode, bypass mode will be entered.
• The frequency of TCK must be lower than that of the peripheral module clock (Pφ). For
details, see section 26, Electrical Characteristics.
• In serial data transfer, data input/output starts with the LSB. Figure 22.5 shows serial data
input/output.
• If the H-UDI serial transfer sequence is disrupted, a TRST reset must be executed. Transfer
should then be retried, regardless of the transfer operation.
• The TDO output timing is from the rise of TCK.
• In the Shift-IR state, the lower 2 bits of the output data from TDO (the IR status word) may not
always be 01.
• If more than 32 bits are serially transferred, serial data exceeding 32 bits output from TDO
should be ignored.
• The TDI pin must not be in the high-impedance state.
TDI
SDIR, SDSR,
SDDRH/SDDRL
31
30
Shift register
Serial data
input/output is in
LSB-first order.
1
0
TDO
Figure 22.5 Serial Data Input/Output
Rev.4.00 Mar. 27, 2008 Page 704 of 882
REJ09B0108-0400